The present invention relates to the sensing of integrated memory circuits, typically Read Only Memories (ROMs), and more particularly to a combined sense amplifier and latching circuit that has high growability and porosity capabilities.
The problem is to read the data contained in a ROM array which may be built out of a 2-dimension matrix of cells, each comprised of one transistor, connected to a series of bit lines (BLs) arranged in columns. Conventionally, a sense amplifier senses the bit line of a column to read the data stored in the selected transistor. With standard sense amplifiers, the data out is not valid during the whole period between two READ operations, and in particular, at the beginning of the access cycle, when the sense amplifier output node is restored to the most positive voltage. Should the data out be required valid at any time, a latch circuit should be added to the sense amplifier. In addition, such a latch circuit becomes absolutely necessary, when the sense circuitry must comply with LSSD rules which require a latched data out. LSSD (Level Sensitive Scan Design) is a test technique that was invented by E. B. Eichelberger and described in U.S. Pat. Nos. 3,783,254, 3,784,907 and 3,961,252 assigned to the assignee of the present invention. This test technique permits every functional element (e.g. a circuit entity or macro such as a RAM, a ROM, an ALU, . . . embedded in a semiconductor chip) to be completely tested and even allows a complex system or the whole machine to be diagnosed at a customer's site by a field-service engineer. A comprehensive survey of the LSSD technique is given in an article entitled "Level-Sensitive Scan Design tests Chips, Boards, Systems" by Neil C. Berglun published in Electronics, Mar. 15, 1979, pp. 108-110.
A LSSD chip comprises several logic blocks, each of which is associated with a storage cell typically a Shift Register Latch (SRL). A single long shift register termed an "LSSD chain" is formed by chaining a number of such SRLs. Each SRL consists of a pair of bistable latches designated L1 and L2.
The L1 latch can be set, one of two inputs, chosen by pulsing one of two different clock signals Ac and Cc, the latter being derived from the system clock signal. Latch L1 also has a data input, called Data In (DI) and a test input called Scan Data In (SDI or SI). Latch L2 has a data input connected to one of the outputs of the associated L1 latch, which receives the Bc clock signal causing the output data or data out (DO) stored in the L1 latch to be transferred into the L2 latch.
The long shift register mentioned above is formed by connecting the output of the L2 latch of the first SRL (therefore forming the first stage of LSSD chain) to the input of the L1 latch of the next SRL, and so on, till the last SRL is connected. The test input SI of the L1 latch in the first SRL is connected to the SI input, or main SI input, of the chip. Test patterns consisting of binary words are applied to the main SI input of the chip. The output of the L2 latch in the last SRL is connected to a Scan Data Out (SDO or SO) output, or main SO output of the chip. The Ac, Bc and Cc clock signals of each SRL are connected to their respective inputs on the chip. Obviously, the "chain" concept is also applicable to functional elements of the same type or of different types.
It should be noted, that while the latches forming the LSSD chains may represent as much as 10% of the surface area of a logic chip, most of these are used to implement the normal system function.
Data is transferred through the SRL in two steps. A binary data applied to the test input Si of latch L1 is first loaded therein by the Ac clock pulse. At the occurrence of the Bc clock pulse, the data becomes available at the output of the L2 latch. A number of pairs of Ac and Bc clock pulses equivalent to the number of SRLs is therefore required in an appropriate sequence to transfer the data to the SO main output of the functional element. In this mode of operation, clock signal Cc is not active.
FIG. 1A shows a typical sensing circuit scheme referenced 10 of the prior art that provides a latched data out to fully comply with LSSD rules.
Now turning to FIG. 1A, circuit 10 basically comprises five blocks: a multiplexer 11, a restore circuit 12, a sense amplifier 13 and first and second LSSD latch circuits 14 and 15. Broadly, latch circuits 14 and 15 respectively correspond to latches L1 and L2 mentioned above. Multiplexer 11 has a conventional structure with four Positive Field-Effect Transistors (PFETs) P1 to P4, with each gate electrode controlled respectively by a corresponding control signal, BS1 to BS4. Each source region of PFETs P1 to P4 is respectively connected to a bit line, BL1 to BL4, while their drain, regions are connected at node A. The interconnection line between node A and the input terminal 16 of sense amplifier 13 is referred to as the data line DL. A restore circuit 12 which simply consists of PFET P5 is connected between node A and a first supply voltage Vdd for restoring node A to a high state. The RESTORE signal, RST, is applied to the gate electrode of PFET P5.
Sense amplifier 13 essentially consists of a double-ended gated latch formed by two inverters I1 and I2 respectively constituted by FET devices P6 and N1 for inverter I1 and P7 and N2 for inverter I2. The inverters I1 and I2 are appropriately cross-coupled in a standard manner, and combined with a gating circuit formed by inverter I3, to form the latch referred to as the sense amplifier latch SAL with internal nodes B and C. The source regions of PFETs P6 and P7 are tied to the first supply voltage Vdd. The source regions of Negative Field-Effect Transistors (NFETs) N1 and N2 are connected to the common node D of the inverter I3 consisting of FET devices P8 and N3. Inverter I3 is connected between the first supply voltage Vdd and a second supply voltage, usually the ground GND. Inverter I3 is driven by a Sense Amplifier Enable (SAE) signal and operates as the gating circuit to connect node D either to Vdd (to render latch SAL inoperative) or to GND (to set the latch), depending on the level of the SAE signal. Nodes B and C are connected respectively to the data line DL and to Vdd through access PFETs P9 and P10. Both PFETs P9 and P10 have their gate electrodes driven by the SAE signal. PFETs P9 and P10 are typical of the double-ended structure of sense amplifier 13. Such sense amplifiers are often implemented in present high performance designs, because when built with large FET devices they can operate at high speeds.
Optionally, sense amplifier 13 further includes two output drivers formed by inverters I4 and I5. They are each formed from a pair of large complementary FET devices. The IN PHASE Vout and OUT OF PHASE Vout output signals are respectively available at terminals 17 and 17' of sense amplifier 13. The OUT OF PHASE signal may not be required by inverter I5 but is nevertheless required to balance the effect of inverter I4 on latch SAL.
The LSSD data out latch circuits 14 and 15 are conventional circuits. Their respective input terminals are referenced 18 and 18' and generate the +L1 and +L2 data out signals at respective output terminals 19 and 19'. In addition, they also respectively deliver the Scan Data In (SI) and Scan Data Out (SO) signals mentioned above. The first latch circuit 14 includes a transmission gate TG1 controlled by the Cc/Cc clock signals, connected between input terminal 18 and a gated-loop latch L1 at node E. The gated-loop latch L1 basically consists of two inverters I6 and I7 with node F coupled therebetween and a loop controlled by PFET P11 whose gate electrode is driven by either the Ac or the Cc clock signal. First latch circuit 14 further includes the Scan Data In (SI) signal generating circuit connected at node E, which simply consists of transmission gate TG2 controlled by the Ac/Ac clock signals. Usually, an inverter I8, connected to node F, is the output buffer which supplies the +L1 data out signal at output terminal 19. The second latch circuit 15 is similar in construction. The transmission gate TG3 is connected between input terminal 18' and the gated loop latch L2 at node G. It is controlled by the Bc/Bc clock signals. The gated loop latch L2 consists of inverters I9 and I10 connected in series with node H coupled therebetween. PFET P12 in the loop is controlled by the Bc clock signal. Optionally, inverter I11 coupled to node H supplies the +L2 data out signal at terminal 19'. As is apparent from FIG. 1A the Scan Data Out (SO) signal is also available at the output of inverter I10. Additional inverters generate the complementary clock signals (Ac, Bc, Cc) that are required for an adequate operation of circuit 10 of FIG. 1A.
FIG. 1B shows the schematic block diagram of the circuit. It is simplified representation of FIG. 1A. Switching devices including inverters and transmission gates are represented by switches with their respective gating/clocking signals. In FIG. 1B, the Scan Data In circuit has been removed from the latch circuit 14, making more apparent that the LSSD latch circuits 14 and 15 have the same basic hardware construction.
Let us now briefly explain the global functionality of circuit 10 of FIGS. 1A/1B during a READ operation in conjunction with FIG. 1C which shows the waveforms at different nodes/terminals of circuit 10. One out of four PFETs P1 to P4 is activated, by one of the control signals BS1 to BS4 provided by the bit line decoder circuit (not represented). Thus, the input signal of the selected bit line is applied to sense amplifier 13 via the activated PFET and data line DL. The potential on the data line DL is sensed through PFET P9 and compared to the supply voltage Vdd through PFET P10. Two cases must be considered depending on whether the value of the binary data stored in the ROM cell or transistor is a "0" or "1":
1. Assuming the value of the data is "0", under control of the system clock (which has selected a word line), the potential of data line DL drops from voltage Vdd to a lower potential. At the transition of the SAE signal to a negative slope (also derived from the system clock), PFETs P9 and P10 are rendered conductive, thus the potential of node B decreases. While the potential of node C remains at voltage Vdd. At this moment, the Vout signal is not representative of valid data. When the SAE signal increases again, PFETs P9 and P10 turn OFF and NFET N3 turns ON, thus setting the sense amplifier latch SAL. As a result, the potential of the B and D nodes go to the ground potential through NFETs N1 and N3 respectively, while the C node remains at voltage Vdd because PFET P7 is ON and PFETs P8 and P6 are OFF. The sense amplifier latch SAL stores the "0" and the Vout signal is at ground. At the transition of clock signal Cc to a positive slope, the "0" is transferred to latch L1 via the transmission gate TG1. As is apparent from the left part of FIG. 1C, the L1 signal and the Vout signal are at the potential of ground (0 Volt).
2. Assuming the value of the data is "1", the potential of the data line DL remains high at voltage Vdd. After setting the sense amplifier latch SAL by the transition of the SAE signal to a negative slope, both B and C nodes still remain at voltage Vdd. When the SAE signal rises, the potential of node D goes to ground through NFET N3. Because the NFET N2 channel length is designated to be shorter than that of N1, the C node will be pulled down to the ground faster than the B node. The B node is held to voltage Vdd through PFET P6. Note by the way, that NFETs N1 and N2 must have different sizes for correct operation. The Vout signal is held at voltage Vdd. At the transition of clock signal Cc to a positive slope, the "1" is transferred to latch L1. As is apparent from 1C, the L1 and Vout signals are at the potential of Vdd after the clock signal Cc reaches its maximum value.
Thus, in both cases, when the SAE signal has increased to its maximum value, the data is latched in the sense amplifier latch SAL. The rising edge of the Cc clock signal transfers the data in latch L1. During the RESTORE mode, which starts immediately after the rising edge of the SAE signal, the potential of the data line DL is restored to voltage Vdd via PFET P5 under control of the RST signal, while the data out is transferred from the sense amplifier latch SAL to the latch L1. Finally, irrespective of whether the value of the data is a "1" or a "0", the data out is transferred from latch L1 to latch L2 at the rising edge of clock signal Bc.
However, although circuit 10 of FIGS. 1A/1B is implemented with a potentially high performance sense amplifier, it exhibits several disadvantages.
First of all, it is very difficult to adjust the gating of sense amplifier 13 and L1 latch circuit 14, because there are three gating/clocking signals, SAE, Ac and Cc as clearly apparent from FIG. 1B. Should growability be required, it would be therefore necessary to have different macros or books (the circuit including the ROM array and the control circuits thereof such as sense amplifier latches decoders, . . . etc.) in the macro/book library, to adapt gating/clocking signal distribution for each macro.
By growability, it is meant the ability of a circuit to adapt to different sizes and specifications as required by the user's application.
Secondly, sense amplifier latch. SAL, to attain high performance, must have a high gain, therefore requiring the use of large devices. It is known that use of large devices result in a bad noise immunity, in other words making the latch SAL too sensitive to porosity. By porosity, it is meant effects due to coupling between signal lines passing above the circuit. As a matter of fact, large devices are known to have a small threshold voltage (e.g. PFET P7 which is a large device has a VT of about 0.3 V), thereby reducing the noise margin, and finally vulnerable to porosity. On the other hand, these large devices must be adjustable for adaptation to the size of a determined ROM macro, and therefore also severely constrain growability.
Moreover, the sense amplifier latch SAL is very sensitive to process misalignment because NFETs N1 and N2 must have different sizes (i.e. different widths W or lengths L). Because NFET N1 must be slower than NFET N2, it must have a smaller width or a larger length. Should the N1 channel length be made shorter than that of N2 during the manufacturing process, NFET N1 would become faster than NFET N2. As a result, in the case where both nodes B and C are held to voltage Vdd as is possible when a "1" is to be read as explained above, the latch will switch in the wrong direction and store false data. In addition, the SAE gating signal, simultaneously drives devices of different types. For example, PFET P9 and NFET N3 have to be simultaneously driven, but they operate at different speeds due to the different mobility of their carriers. Because the sense amplifier latch SAL of FIG. 1A operates with signal transitions at the time of set up, an accurate control of these devices is not easy.
Finally, for all the reasons mentioned above, circuit 10 is not appropriate, in particular for growability and for porosity constraints, that are required for modern sense amplifiers complying with LSSD rules. In addition, its potential from a performance point of view cannot be fully exploited due to its high gain; the noise margin reduction that would result from this high gain would be unacceptable.